1. Field of the Invention
The present invention relates to an instruction execution circuit.
2. Description of the Related Art
Today, electronic devices which incorporate an instruction execution circuit in which a processor reads and executes an instruction of a program stored in a memory circuit such as memory are used in various fields.
In the audio field, for example, electronic devices which perform processing such as compression, data processing, reproduction and the like of sound, which was made into digital data, by execution of the program by the processor, are widely spread.
If sound is handled as digital data, in order to reduce the data amount, digital data is encoded in accordance with a predetermined standard and decoded in reproduction in general. MP3, WMA, AAC and the like are known as the standards of encoding and decoding.
In this case, the processor performs encoding and decoding processing by sequentially reading out instructions of a program for encoding and decoding from a memory circuit and executing the same. Various such technologies for encoding and decoding have been developed (See Japanese patent Laid-Open No. 2009-230773, for example).
By referring to an instruction execution circuit 1010 illustrated in FIGS. 4 to 6, a flow of decoding processing by a processor 100 will be described.
Memory 200 stores a plurality of instructions included in a program for performing decoding. Also, the processor 100 performs decoding processing by executing each instruction stored in the memory 200. The processor 100 and the memory 200 are operated in synchronization with a clock signal outputted from a clock generation circuit 500.
In general, the processing of decoding encoded data generated by encoding digital sound data is performed by the unit of data called frame. After the processor 100 decodes the encoded data for one frame, the processor 100 does not start decoding of the encoded data of the subsequent frame in a row but waits for completion of reproduction of the previously decoded digital data and then, starts decoding of the encoded data of the subsequent frame. Therefore, the processor 100 repeatedly executes the decoding program illustrated in FIG. 6 by the frame.
The processor 100 outputs a value of an address where the instruction is stored to an address bus in the order of execution of the instructions included in this program. The value of the address is calculated by a program counter, not shown, provided in the processor 100. The address outputted from the processor 100 is inputted into the memory 200 and an address decoder 410.
When the address is inputted, the address decoder 410 outputs an enable signal (CE. An inverse sign is omitted. The same applies to the following.) to the memory 200.
The memory 200 outputs the instruction stored at the inputted address to the data bus while the enable signal is inputted.
Then, the processor 100 obtains the instruction outputted to the data bus and executes the instruction.
When the processor 100 sequentially executes the above processing for each instruction included in the program, the encoded data for one frame is decoded.
As illustrated in FIG. 6, the program for performing decoding starts with an “LD R1” instruction indicated by a label reading “START:” and ends with a “JUMP WAIT” instruction. However, a jump destination of the “JUMP WAIT” is a “NOP” instruction indicated by a label reading “WAIT:”.
Thus, after decoding of the encoded data for one frame is finished, the processor 100 waits for completion of reproduction of the digital data of the frame by repeatedly reading out and executing the “NOP” instruction and the “JUMP WAIT” instruction.
When the reproduction of the digital data of the frame is completed, as illustrated in FIG. 5, an interrupt signal is inputted into the processor 100. Then, the processor 100 starts sequential execution of each instruction from the “LD R1” instruction indicated by the label reading “START:” again so as to start decoding of the encoded data of the subsequent frame.
A data amount of the encoded data in one frame varies with a bit rate or sampling frequency designated when the digital sound data is encoded, and time required for decoding the encoded data in one frame varies with the bit rate or sampling frequency. Thus, latency time until the reproduction of the previously decoded digital data is completed varies with the bit rate or sampling frequency.
When a case with a large data amount in one frame is compared with a case with a small data amount, as illustrated in FIG. 4, if the data amount in one frame is large (case A), decoding requires long time for that portion, and the latency time becomes short, while if the data amount in one frame is small (case B), decoding requires only short time, and the latency time becomes long.
As described above, until the reproduction of the decoded digital data is completed, the processor 100 repeatedly reads and executes the “NOP” instruction and the “JUMP WAIT” instruction. Therefore, the instruction execution circuit 1010 illustrated in FIG. 5 consumes power even during the latency time.
The electronic devices which can handle sound as such digital data have spread in the forms of portable phones, portable music players, IC recorders, on-board music players and the like. Many of these electronic devices are operated by power from a battery, and suppression of power consumption is in strong demand.
Also, the demand for power saving is strong not only for the audio electronic devices but also for the electronic devices incorporating an instruction execution circuit provided with a processor and a memory circuit.
The present invention was made in view of the above problems and has an object to reduce power consumption of an instruction execution circuit provided with a memory circuit storing a program and a processor executing the program.